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Saleem Abdulrasool
Demangle: correct demangling for CV-qualified functions

When demangling a CV-qualified function type with a final reference type
parameter, we would treat the reference type parameter as a r-value ref
accidentally.  This would result in the improper decoration of the
function type itself.

Resolves PR31741!
Saleem Abdulrasool
Demangle: use named values for CV qualifiers

Rather than hard-coding magic values of 1, 2, 4 (bit-field), use an enum
to name the values.  NFC.
Ivan Krasin
Revert [AMDGPU][mc][tests][NFC] Add coverage/smoke tests for Gfx7 and Gfx8.

Reason: broke ASAN bots with a global buffer overflow.

Each test contains 20-30K test cases but takes only several (from 4 to 10)
seconds to complete on average machine. The tests cover the majority of
AMDGPU Gfx7/Gfx8 instructions, including many dark corners, and intended
to quickly find out if something is broken.
Saleem Abdulrasool
cxa_demangle: fix rvalue ref check

When checking if the type is a r-value ref, we would not do a complete
check.  This would result in us treating a trailing parameter reference
`&)` as a r-value ref, and improperly inject the cv qualifier on the
type.  We now correctly demangle the type `KFvRmE` as a constant
function rather than a constant reference.

Fixes PR31741!
Peter Collingbourne
IRGen: Factor out function CodeGenAction::loadModule. NFCI.
Daniel Berlin
Remove the load hoisting code of MLSM, it is completely subsumed by GVNHoist

GVNHoist performs all the optimizations that MLSM does to loads, in a
more general way, and in a faster time bound (MLSM is N^3 in most
cases, N^4 in a few edge cases).

This disables the load portion.

Note that the way ld_hoist_st_sink.ll is written makes one think that
the loads should be moved to the while.preheader block, but

1. Neither MLSM nor GVNHoist do it (they both move them to identical places).

2. MLSM couldn't possibly do it anyway, as the while.preheader block
is not the head of the diamond, while.body is.  (GVNHoist could do it
if it was legal).

3. At a glance, it's not legal anyway because the in-loop load
conflict with the in-loop store, so the loads must stay in-loop.

I am happy to update the test to use update_test_checks so that
checking is tighter, just was going to do it as a followup.

Note that i can find no particular benefit to the store portion on any

Peter Collingbourne
IRGen: Factor out function clang::FindThinLTOModule. NFCI.
Marshall Clow
Add a test to make sure that implicit conversion from error_code to bool will fail
Richard Smith
[docs] Add TableGen-based generator for command line argument documentation,
and generate documentation for all (non-hidden) options supported by the
'clang' driver.
Marshall Clow
Update status for LWG2733
Changpeng Fang
AMDGPU/SI: Give up in promote alloca when a pointer may be captured.

Differential Revision:

Saleem Abdulrasool
Demangle: avoid butchering parameter type

When demangling a CV-qualified function type with a final parameter with
a reference type, we would insert the CV qualification on the parameter
rather than the function, and in the process adjust the insertion point
by one extra, splitting the type name.  This avoids doing so, even
though the attribution is still incorrect.
Mehdi Amini
Fix test/Driver/embed-bitcode.c on non-Darwin host by setting the target explicitly
Saleem Abdulrasool
cxa_demangle: avoid butchering the last parameter type

Fix an off-by-one case which would destroy the final parameter in a
CV-qualified function type with a reference.  We still get the CV
qualification incorrect, but at least we do not clobber the type name
any longer.

Partially fixes PR31741.
Marshall Clow
Implement LWG2733: [fund.ts.v2] gcd / lcm and bool.  We already did tbis for C++17, so replicate the changes in experimental.
Mehdi Amini
Forward -bitcode_process_mode to ld64 in marker-only mode

Reviewers: steven_wu

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D29066
Mehdi Amini
Split isUsingLTO() outside of embedBitcodeInObject() and embedBitcodeMarkerOnly().

Summary: These accessors maps directly to the command line option.

Reviewers: steven_wu

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D29065
Chad Rosier
[AArch64] Fix typo. NFC.
Marshall Clow
Mark LWG2736 as complete. No code changes, but we have more tests now
Amaury Sechet
Use InstCombine's builder in foldSelectCttzCtlz instead of creating a new one.

Summary: As per title. This will add the instructiions we are interested in in the worklist.

Reviewers: mehdi_amini, majnemer, andreadb

Differential Revision: https://reviews.llvm.org/D29081
Stanislav Mekhanoshin
[AMDGPU] Add VGPR copies post regalloc fix pass

Regalloc creates COPY instructions which do not formally use VALU.
That results in v_mov instructions displaced after exec mask modification.
One pass which do it is SIOptimizeExecMasking, but potentially it can be
done by other passes too.

This patch adds a pass immediately after regalloc to add implicit exec
use operand to all VGPR copy instructions.

Differential Revision: https://reviews.llvm.org/D28874
Reid Kleckner
Fix pc_array bounds check to use elements instead of bytes

pc_array_size and kPcArrayMaxSize appear to be measured in elements, not
bytes, so we shouldn't multiply idx by sizeof(uptr) in this bounds
check.  32-bit Chrome was tripping this assertion because it has 64
million coverage points. I don't think it's worth adding a test that has
that many coverage points.
Evandro Menezes
[AArch64] Rename 'no-quad-ldst-pairs' to 'slow-paired-128'

In order to follow the pattern of the existing 'slow-misaligned-128store'
option, rename the option 'no-quad-ldst-pairs' to 'slow-paired-128'.
Chris Bieneman
[Lanai] Rename LanaiInstPrinter library to LanaiAsmPrinter

    This is in keeping with LLVM convention. The classes are InstPrinters, but the library is ${target}AsmPrinter.

This patch is in response to bryant pointing out to me that Lanai was the only backend deviating from convention here. Thanks!

Reviewers: jpienaar, bryant

Subscribers: mgorny, jgosnell, llvm-commits

Differential Revision: https://reviews.llvm.org/D29043
Sanjay Patel
[InstSimplify] try to eliminate icmp Pred (add nsw X, C1), C2

I was surprised to see that we're missing icmp folds based on 'add nsw' in InstCombine,
but we should handle the InstSimplify cases first because that could make the InstCombine
code simpler.

Here are Alive-based proofs for the logic:

Name: add_neg_constant
Pre: C1 < 0 && (C2 > ((1<<(width(C1)-1)) + C1))
%a = add nsw i7 %x, C1
%b = icmp sgt %a, C2
%b = false

Name: add_pos_constant
Pre: C1 > 0 && (C2 < ((1<<(width(C1)-1)) + C1 - 1))
%a = add nsw i6 %x, C1
%b = icmp slt %a, C2
%b = false

Name: nuw
Pre: C1 u>= C2
%a = add nuw i11 %x, C1
%b = icmp ult %a, C2
%b = false

Differential Revision: https://reviews.llvm.org/D29053